Traditionally, integrated circuit (IC) transistors have employed a planar design wherein components of the transistor—source, drain, and channel—are formed in the surface of the semiconductor substrate, and the gate component is formed as a flat structure atop the channel region of the substrate's surface. More recently, however, the desire for smaller and smaller device sizes has motivated the development of so-called 3-D transistors wherein source, drain, and channel are formed in fin-shaped structures which extend vertically from the substrate surface, generally with a high aspect ratio. With the channel formed in these vertical fin structures, the gate component of a 3-D transistor can be made to wrap around the channel region, substantially increasing the surface area of the channel region relative to its volume exposed directly to the gate voltage.
The structural differences between planar and 3-D transistors is schematically illustrated in FIGS. 1A and 1B. FIG. 1A schematically illustrates a traditional planar IC transistor 100. On the left in the figure is a side view showing source 120, channel 130, and drain 140 formed in a silicon substrate 110, with gate 150 sitting atop channel 130 separated by gate dielectric 149. To the right in the figure is a cross-sectional view of the same transistor 100 taken from the point-of-view of the vertical dotted line (as indicated by the horizontal arrow). From both views, it is seen that gate 150 is only located adjacent to one side of channel 130 (separated by gate dielectric 149). FIG. 1B provides a simplified illustration of a modern 3-D transistor design 101 with side view (left) and cross-sectional view (right) similar to that shown in FIG. 1A for the planar transistor 100. It is seen from the side view that source 121, channel 131, and drain 141 extend vertically from the plane of the silicon substrate 110 (unlike planar transistor 100). However, the cross-sectional view in FIG. 1B (right) shows that gate 151 of 3-D transistor 101 is able to wrap around the channel region 131 from three sides (in contrast to the arrangement of the gate 150 in planar transistor 100). This wrapping of the gate around the vertical fin structure is further illustrated in FIG. 1C (again showing 3-D transistor 101 with source 121, drain 141, and gate 151, although channel 131 is obscured by the gate); and FIG. 1D illustrates how multiple 3-D transistors 101 formed from parallel vertical fin structures may be wrapped by a 3-D gate component 151. This fundamental shift in transistor architecture from planar to 3-D designs has created challenges for IC fabrication, and to optimally address these challenges new fabrication techniques must be developed.